Design and FPGA Implementation of High-speed Parallel FIR Filters
Baolin Hou, Yuancheng Yao, Mingwei Qin
Available Online April 2015.
- https://doi.org/10.2991/icmra-15.2015.189How to use a DOI?
- FIR Filter; Field Programmable Gate Array Implementation; High-speed Parallel Algorithm; Unfold.
- This paper proposes a novel design method of parallel Finite Impulse Response (FIR) filter, which structure is parallel transposed. It can increase the running speed by M times compared with the serial FIR filter, where the M is the number of sub-filters, and the parallel FIR filter only introduces very small delay. Firstly the theoretical foundation of parallel FIR filters is analyzed. An example of the floating point parallel transposed FIR band-pass filter is given to verify the algorithm. Then a parallel transposed FIR band-pass filter is designed, which has optimum fixed point coefficients. Finally the fixed point of this filter is implemented in Xilinx’s Virtex-6 Field Programmable Gate Array (FPGA). According to the simulation results, this filter has smaller resource consumption and its sampling rate up to 1.2GHz.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Baolin Hou AU - Yuancheng Yao AU - Mingwei Qin PY - 2015/04 DA - 2015/04 TI - Design and FPGA Implementation of High-speed Parallel FIR Filters BT - 3rd International Conference on Mechatronics, Robotics and Automation PB - Atlantis Press SP - 975 EP - 979 SN - 2352-538X UR - https://doi.org/10.2991/icmra-15.2015.189 DO - https://doi.org/10.2991/icmra-15.2015.189 ID - Hou2015/04 ER -