Eliminate the X-Optimization during RTL Verification
Xu Huang, He Xin, Lintao Liu, Luncai Liu
Available Online April 2015.
- https://doi.org/10.2991/icmra-15.2015.75How to use a DOI?
- Verification of complex SoC designs suffers from X-optimization issues that often conceal design bugs. The deployment of low power techniques such as power-shutdown in today’s SoC designs exacerbate these X-optimism issues. To address these problems we adopted a new simulation semantic that more accurately models non-deterministic values in logic simulation. In this paper we discuss how to eliminate the X-optimism during RTL verification.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Xu Huang AU - He Xin AU - Lintao Liu AU - Luncai Liu PY - 2015/04 DA - 2015/04 TI - Eliminate the X-Optimization during RTL Verification BT - 3rd International Conference on Mechatronics, Robotics and Automation PB - Atlantis Press SP - 381 EP - 385 SN - 2352-538X UR - https://doi.org/10.2991/icmra-15.2015.75 DO - https://doi.org/10.2991/icmra-15.2015.75 ID - Huang2015/04 ER -