A 16b 4GSPS Two-Times Interleaved DAC with INL ≤±2.9LSB
- https://doi.org/10.2991/icmmita-16.2016.117How to use a DOI?
- dual-channels; two-times interleaved; quartered switches
A two-times interleaved DAC in a standard 65nm CMOS technology is presented with a data-clock frequency of 4GHz with INL ≤±2.9LSB. Since two DACs are placed in parallel, their output current goes to the DAC multiplexer, which alternatively connects one DAC to the output, and the other one to an identical dummy output. The two-times interleaved DAC with quartered switches increases the overall data of two times and reduces the complexity of the design effectively while suppressing the non- idealities.
- © 2017, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Hai Dong AU - Zongmin Wang AU - Ying Kong AU - Xinmang Peng PY - 2017/01 DA - 2017/01 TI - A 16b 4GSPS Two-Times Interleaved DAC with INL ≤±2.9LSB BT - Proceedings of the 2016 4th International Conference on Machinery, Materials and Information Technology Applications PB - Atlantis Press SP - 635 EP - 639 SN - 2352-538X UR - https://doi.org/10.2991/icmmita-16.2016.117 DO - https://doi.org/10.2991/icmmita-16.2016.117 ID - Dong2017/01 ER -