Synchronization of JESD204B-based ADCs

DOI

10.2991/icmmbe-16.2016.3How to use a DOI?

Keywords

JESD204B, deterministic latency, synchronization, Radar system

Abstract

With the rapid development of radarsignal processing systems, a great demand of high-speed communication is required. JESD204B interface has become an outstanding solution for ADC-related data transmission, and has been widely applied. However, the synchronization of multiply JESD204B-based ADCs has been a challenge because of the special feature such as deterministic latency. In this paper, we design a data acquisition system integrated two JESD204B-based ADCs, and proposed a general and flexible synchronization method based on FPGA, by using and controlling deterministic latency. As is validated by the practical measurements,the method can maintainaphase difference between the two 2.5Gbps ADCsfrom17ps to 22psstably, forthe signals of frequencies less than 1.8GHz.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Tao Yan
AU  - Shanqing Hu
AU  - Xingming Li
PY  - 2016/09
DA  - 2016/09
TI  - Synchronization of JESD204B-based ADCs
BT  - Proceedings of the6th International Conference on Mechatronics, Materials, Biotechnology and Environment (ICMMBE 2016)
PB  - Atlantis Press
SP  - 9
EP  - 14
SN  - 2352-5401
UR  - https://doi.org/10.2991/icmmbe-16.2016.3
DO  - 10.2991/icmmbe-16.2016.3
ID  - Yan2016/09
ER  -