The Design of High Speed Data Acquisition System Based on JESD204B

DOI

10.2991/iccia-17.2017.145How to use a DOI?

Keywords

Data acquisition system, JESD204B interface, High-speed ADC.

Abstract

Recently, various acquisition systems require data converters to provide higher resolution and sampling rates. The physical layout of parallel interfaces and the bit rate limitations of serial LVDS methods pose technical hurdles for designers. The design is based on the classical architecture of FPGA+DSP+ADC of data acquisition system. The High speed ADC is based on JESD204B interface with four slices and two channels, it can meet the requirements of high-speed acquisition, and high-speed sampling of eight channels. It provides a good method for the design and application of various high-speed acquisition systems, and it effectively solves all kinds of problems in parallel transmission of traditional data acquisition, and brings great engineering application value.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yu Wang
AU  - Qingzhan Shi
AU  - Qi Feng
PY  - 2016/07
DA  - 2016/07
TI  - The Design of High Speed Data Acquisition System Based on JESD204B
BT  - Proceedings of the 2nd International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2017)
PB  - Atlantis Press
SP  - 824
EP  - 828
SN  - 2352-538X
UR  - https://doi.org/10.2991/iccia-17.2017.145
DO  - 10.2991/iccia-17.2017.145
ID  - Wang2016/07
ER  -