A CMOS input buffer with linearization technique for high-speed A/D
- 10.2991/ic3me-15.2015.175How to use a DOI?
- Input Buffer, Linearization Technique, High-speed A/D
A CMOS input buffer with linearization technique for high-speed A/D is introduced. The buffer features high-linearity and low-power consumption. The simulation shows that the SFDR of the buffer is up to 107dB at an input clock of 250MHz with an input signal of 10MHz. A 14-bit 250MSPS pipelined A/D converter integrated this buffer improves its distortion by 5-10 dB.
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Xi Chen AU - Liang Li AU - Mingyuan Xu AU - Xiaofeng Shen PY - 2015/08 DA - 2015/08 TI - A CMOS input buffer with linearization technique for high-speed A/D BT - Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering PB - Atlantis Press SP - 918 EP - 921 SN - 2352-5401 UR - https://doi.org/10.2991/ic3me-15.2015.175 DO - 10.2991/ic3me-15.2015.175 ID - Chen2015/08 ER -