A 1.8V 12-bit 1GS/s SiGe BiCMOS time-interleaved Analog-to-Digital converter
- https://doi.org/10.2991/ic3me-15.2015.176How to use a DOI?
- pipelined ADC, time-interleaved, recode Calibration
This paper describes a 1.8V 12 bit 1 GS/s pipeline ADC realized in a 0.18 m BiCMOS SiGe process. The ADC consists of a two-way time-interleaved hierarchical structure. Each sub-ADC consists of one input buffer and T&H with BiCMOS technology which improves the dynamic performance and reduces the converter error rate. The interleaving spurs caused by channel mismatch use OTPNVM to recode calibration. It achieves an SFDR of 87dB at 200MHz. Spectre simulation shows that the spurs of the channel mismatch achieve less than -106dB at gain and timing error, -97dB at the offset error.
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Mingyuan Xu AU - Liang Li AU - Xiaofeng Shen AU - Xi Chen PY - 2015/08 DA - 2015/08 TI - A 1.8V 12-bit 1GS/s SiGe BiCMOS time-interleaved Analog-to-Digital converter BT - Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering PB - Atlantis Press SP - 922 EP - 925 SN - 2352-5401 UR - https://doi.org/10.2991/ic3me-15.2015.176 DO - https://doi.org/10.2991/ic3me-15.2015.176 ID - Xu2015/08 ER -