Design and Implementation of Nanosecond Pulse Generator Based on Reconfiguration PLL in FPGA

Yu Zhu; Lianming Wang

doi:10.2991/esac-15.2015.78

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Design and Implementation of Nanosecond Pulse Generator Based on Reconfiguration PLL in FPGA

Authors

Yu Zhu, Lianming Wang

Corresponding Author

Yu Zhu

Available Online August 2015.

DOI: 10.2991/esac-15.2015.78 How to use a DOI?
Keywords: Field programmable gate array (FPGA), Phase-locked loop (PLL), Dynamic reconfiguration, Nanosecond pulse
Copyright: © 2015, the Authors. Published by Atlantis Press.
Open Access: This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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Volume Title: Proceedings of the 2015 International Conference on Electronic Science and Automation Control
Series: Advances in Computer Science Research
Publication Date: August 2015
ISBN: 978-94-62520-95-0
ISSN: 2352-538X
DOI: 10.2991/esac-15.2015.78 How to use a DOI?
Open Access: This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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ris enw bib

TY  - CONF
AU  - Yu Zhu
AU  - Lianming Wang
PY  - 2015/08
DA  - 2015/08
TI  - Design and Implementation of Nanosecond Pulse Generator Based on Reconfiguration PLL in FPGA
BT  - Proceedings of the 2015 International Conference on Electronic Science and Automation Control
PB  - Atlantis Press
SP  - 323
EP  - 326
SN  - 2352-538X
UR  - https://doi.org/10.2991/esac-15.2015.78
DO  - 10.2991/esac-15.2015.78
ID  - Zhu2015/08
ER  -

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