Design of Digital Geophone System Based on FPGA

DOI

10.2991/esac-15.2015.15How to use a DOI?

Keywords

Digital geophone, FPGA, Acquisition system, 24-bit - ADC

Abstract

In order to meet the needs of high-resolution seismic data acquisition, a kind of 24-bit high performance digital geophone was designed. The digital geophone was designed with a low-power, high-integration FPGA as the acquisition controller, and SOPC embedded system was established to control the whole collection station. This paper gives the overall architecture of the geophone and concrete design and implementation of the system’s main peripheral circuits, including the sensor’s self-test circuit, preamplifier filter circuit, 24-bit analog-to-digital conversion circuit and communication interface circuit. Each of these parts was optimally designed for low power. The system is controlled based on Verilog HDL and Nios II soft core. In this way, the area of circuit board is reduced efficiently, and high speed acquisition and high precision measurement can be realized. Finally, with the use of simulated seismic waves generated by the vibration table, we completed the data acquisition and transmission experiment of the acquisition system containing three collection nodes. The results show that this system is of high precision, high reliability, low power, low cost and it is easy to be upgraded and maintained.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yi Chen
AU  - Donghai Qiao
PY  - 2015/08
DA  - 2015/08
TI  - Design of Digital Geophone System Based on FPGA
BT  - Proceedings of the 2015 International Conference on Electronic Science and Automation Control
PB  - Atlantis Press
SP  - 58
EP  - 61
SN  - 2352-538X
UR  - https://doi.org/10.2991/esac-15.2015.15
DO  - 10.2991/esac-15.2015.15
ID  - Chen2015/08
ER  -