A Modeling Method of Press-Pack IGBT from Chip-level to Module-level

DOI

10.2991/eame-18.2018.23How to use a DOI?

Keywords

insulated gate bipolar transistor(IGBT); press-pack IGBT(PPI); model; parasitic parameter; paralleled operation

Abstract

In press-pack IGBT the currents flowing through paralleled chips are not consistent due to the packaging structure, chip difference, uneven stress distribution and so on. The maximum current overshoot and maximum junction temperature of the internal paralleled chips determine the limitation of the device's application. A hierarchical modeling method based on the geometry structure of press-pack IGBT is proposed in this paper, and a relatively more accurate device model is established, which provides a reliable and practical modeling method for analyzing electrical characteristics of internal branches under different operating conditions. First of all, according to the data sheet or test results, the chip behavior model is built by Saber software; Secondly, parameter extracting software is used to extract the packaging parasitic parameters and the equivalent circuit network is established; Finally, considering the application environment of press-pack IGBT, a nonlinear resistor is introduced to simulate the piezoresistive effect of a semiconductor and the change of component contact resistance caused by stress. The comparison with test data shows that the model is in good agreement with the test results in key parameters and has high precision. Simulation and test results prove the validity of the model and the feasibility of the modeling method.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Shuai Sun
AU  - Meiting Cui
AU  - Zhongyuan Chen
AU  - Xiaodong Luo
AU  - Jinyuan Li
AU  - Huipeng Ren
PY  - 2018/06
DA  - 2018/06
TI  - A Modeling Method of Press-Pack IGBT from Chip-level to Module-level
BT  - Proceedings of the 2018 3rd International Conference on Electrical, Automation and Mechanical Engineering (EAME 2018)
PB  - Atlantis Press
SP  - 115
EP  - 120
SN  - 2352-5401
UR  - https://doi.org/10.2991/eame-18.2018.23
DO  - 10.2991/eame-18.2018.23
ID  - Sun2018/06
ER  -