Digital Hardware Spiking Neuronal Network with STDP for Real-time Pattern Recognition
- 10.2991/jrnal.k.200528.010How to use a DOI?
- SNN; STDP; DSSN; FPGA; ethernet
By mimicking or being inspired by the nervous system, neuromorphic systems are designed to realize robust and power-efficient information processing by highly parallel architecture. Spike Timing Dependent Plasticity (STDP) is a common learning method for Spiking Neural Networks (SNNs). Here, we present a real-time SNN with STDP implementation on Field Programmable Gate Array (FPGA) using digital spiking silicon neuron model. Equipped with Ethernet Interface, FPGA allows online configuration as well as real-time processing data input and output. We show that this hardware implementation can achieve real-time pattern recognition tasks and allows the connection between multi-SNNs to extend the scale of networks.
- © 2020 The Authors. Published by Atlantis Press SARL.
- Open Access
- This is an open access article distributed under the CC BY-NC 4.0 license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - JOUR AU - Yang Xia AU - Timothée Levi AU - Takashi Kohno PY - 2020 DA - 2020/06/02 TI - Digital Hardware Spiking Neuronal Network with STDP for Real-time Pattern Recognition JO - Journal of Robotics, Networking and Artificial Life SP - 121 EP - 124 VL - 7 IS - 2 SN - 2352-6386 UR - https://doi.org/10.2991/jrnal.k.200528.010 DO - 10.2991/jrnal.k.200528.010 ID - Xia2020 ER -