Proceedings of the 9th Joint International Conference on Information Sciences (JCIS-06)

Application of Hardware Architecture of Genetic Algorithm for Optimal Packet Scheduling

Authors
Rong-Hou Wu, Yang-Han Lee, Shiann-Tsong Sheu, Hsien-Wei Tseng, Ming-Hsueh Chuang, Yung-Kuang Wang
Corresponding Author
Rong-Hou Wu
Available Online October 2006.
DOI
10.2991/jcis.2006.299How to use a DOI?
Keywords
Genetic algorithm, Dense Wavelength Division Multiplexing, packet scheduling.
Abstract

In Dense Wavelength Division Multiplexing (DWDM) technologies, the optimal packet scheduling is a common encounter issue in multiple channels network. NP-hard problem deals with finding a way to rearrange packets in multiple channels into a finite and rare channel. Genetic algorithm (GA) is one of the most efficient ways to solve this issue. We hope to find a better solution to our task through the GA characteristics of multiprocessor searching and survivor of the fittest. Therefore, a modified and achievable hardware architecture of GA is presented in this paper. This architecture can increase the schedule speed of packet scheduling also can promote the efficiency of DWDM in Optical Communication Networks.

Copyright
© 2006, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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Volume Title
Proceedings of the 9th Joint International Conference on Information Sciences (JCIS-06)
Series
Advances in Intelligent Systems Research
Publication Date
October 2006
ISBN
10.2991/jcis.2006.299
ISSN
1951-6851
DOI
10.2991/jcis.2006.299How to use a DOI?
Copyright
© 2006, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Cite this article

TY  - CONF
AU  - Rong-Hou Wu
AU  - Yang-Han Lee
AU  - Shiann-Tsong Sheu
AU  - Hsien-Wei Tseng
AU  - Ming-Hsueh Chuang
AU  - Yung-Kuang Wang
PY  - 2006/10
DA  - 2006/10
TI  - Application of Hardware Architecture of Genetic Algorithm for Optimal Packet Scheduling
BT  - Proceedings of the 9th Joint International Conference on Information Sciences (JCIS-06)
PB  - Atlantis Press
SN  - 1951-6851
UR  - https://doi.org/10.2991/jcis.2006.299
DO  - 10.2991/jcis.2006.299
ID  - Wu2006/10
ER  -