High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-ta

DOI

10.2991/jcis.2006.192How to use a DOI?

Keywords

DWT/IDWT, low-power, image coder, JPEG-2000, 4-tap Daubechies filters, multiplierless.

Abstract

This paper presents two architectures for 2-D discrete wavelet transform (DWT) and inverse DWT (IDWT). The first consists of transform module, RAM module and address sequencer. The transform module, which takes uniform and regular structure with local communication, offers many advantages, e.g. simple control flow, full hardware-utilization and low-power. The second architecture features parallel and pipelined computation for high throughput. Both architectures are suitable for VLSI implementations of the wavelet based image coders, e.g. JPEG-2000. The FPGA realization and VLSI implementation of the proposed 2-D DWT/IDWT architectures with 4-tap Daubechies filters shows significant improvements in terms of power saving and chip area.

Copyright

© 2006, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Tze-Yun Sung
PY  - 2006/10
DA  - 2006/10
TI  - High-Speed and Low-Power Architectures for Forward and Inverse Discrete Wavelet Transform Using 4-ta
BT  - Proceedings of the 9th Joint International Conference on Information Sciences (JCIS-06)
PB  - Atlantis Press
SP  - 524
EP  - 527
SN  - 1951-6851
UR  - https://doi.org/10.2991/jcis.2006.192
DO  - 10.2991/jcis.2006.192
ID  - Sung2006/10
ER  -