The Implementation of Fractional Pixel ME in H.264 Video Encoder

DOI

10.2991/icmt-13.2013.211How to use a DOI?

Keywords

H.264. inter-frame. fractional pixel ME.

Abstract

This paper first introduce the H.264 video codec standard briefly, then analyze the inter-frame motion estimation in H.264. After that we propose an optimaized algorithm and the corresponding architecture. A pipeline-architecture was proposed with scaled searching algorithm based on the analysis to the previous work and the consideration of the system requirement between chip area and performance. A pipelined architecture with two 1-dimension interpolation for fractional pixe ME was proposed to meet the needs of SHD 2160P video encoding, resulting in lower complexity and more throughout. Synthesized with Charted 0.13 m process, the design consumed 174.3K logic gates, with peak frequency of about 200MHz, and consumed less than 20mW at the power supply of 1.20V.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Zuo Shikai
AU  - Wang Mingjiang
AU  - Wu Zejun
AU  - Xiao Liyi
PY  - 2013/11
DA  - 2013/11
TI  - The Implementation of Fractional Pixel ME in H.264 Video Encoder
BT  - Proceedings of 3rd International Conference on Multimedia Technology(ICMT-13)
PB  - Atlantis Press
SP  - 1736
EP  - 1745
SN  - 1951-6851
UR  - https://doi.org/10.2991/icmt-13.2013.211
DO  - 10.2991/icmt-13.2013.211
ID  - Shikai2013/11
ER  -