Proceedings of the 2016 4th International Conference on Machinery, Materials and Information Technology Applications

Octopus: A Flexible, Efficient MPSoC Prototype for Non-linear Interference Cancellation

Authors
Luechao Yuan, Chuan Tang, Cang Liu, Zuocheng Xing
Corresponding Author
Luechao Yuan
Available Online January 2017.
DOI
10.2991/icmmita-16.2016.181How to use a DOI?
Keywords
MPSoC; Tomlinson-Harashima; VLSI Design
Abstract

Many non-linear (NL) interference cancellation (IC) algorithms characterize vector based operations instead of matrix operations, and their performance can be further improved by a proper sorted preprocessing of the channel information, e.g., successive interference cancellation (SIC) and Tomlinson-Harashima precoding (THP) for multi-user multiple-input and multiple-output (MIMO) communication systems. However, on the one hand, application-specific architectures are efficient but not flexible in performing NL IC algorithms; on the other hand, existing single-core based flexible architectures aimed for intensive matrix operations are not efficient when mapping these algorithms. Alternatively, the multiprocessor system-on-chip (MPSoC) architecture can provide better diversity to implement demanding NL algorithms. This paper proposes an efficient and programmable MPSoC prototype to bridge the efficiency and flexibility gap, especially for versatile Gram-Schmidt process (GSP) aided NL IC algorithms. This prototype incorporates several slave processors and one master processor based on the division of computing and control of the mapped algorithms. The slave processor integrates a coarse-grained programmable element (CGPE) with special support for atomic vector operations, while the maser processor is responsible for task schedule and data transportation among slave processors and memories. For demonstration, a tightly coupled sorted QR decomposition (SQRD) aided THP is mapped to the proposed MPSoC, where a speculative dynamic runtime schedule (SDRS) strategy is applied to reduce the computational delay. The synthesis results are presented to show the efficiency and feasibility of our MPSoC prototype.

Copyright
© 2017, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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Volume Title
Proceedings of the 2016 4th International Conference on Machinery, Materials and Information Technology Applications
Series
Advances in Computer Science Research
Publication Date
January 2017
ISBN
978-94-6252-285-5
ISSN
2352-538X
DOI
10.2991/icmmita-16.2016.181How to use a DOI?
Copyright
© 2017, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Cite this article

TY  - CONF
AU  - Luechao Yuan
AU  - Chuan Tang
AU  - Cang Liu
AU  - Zuocheng Xing
PY  - 2017/01
DA  - 2017/01
TI  - Octopus: A Flexible, Efficient MPSoC Prototype for Non-linear Interference Cancellation
BT  - Proceedings of the 2016 4th International Conference on Machinery, Materials and Information Technology Applications
PB  - Atlantis Press
SP  - 980
EP  - 988
SN  - 2352-538X
UR  - https://doi.org/10.2991/icmmita-16.2016.181
DO  - 10.2991/icmmita-16.2016.181
ID  - Yuan2017/01
ER  -