Research on Self-biased PLL Technique for High Speed SERDES Chips
- https://doi.org/10.2991/icmmita-15.2015.276How to use a DOI?
- Siphonic self-biased; VCO; PLL; broadband rate Introduction.
This paper is designed for wide input range of SerDes chip phase-locked loop circuit, using self-biased technology, there is a wide range of input reference frequency, the need for external bias circuit, and loop bandwidth can follow input reference frequency changes in noise with good inhibitory effect. Small footprint annular VCO wide frequency adjustment range, and can easily produce the CDR SerDes required multi-phase clock.
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Meidong Lin AU - Zhiping Wen AU - Lei Chen PY - 2015/11 DA - 2015/11 TI - Research on Self-biased PLL Technique for High Speed SERDES Chips BT - Proceedings of the 2015 3rd International Conference on Machinery, Materials and Information Technology Applications PB - Atlantis Press SP - 1498 EP - 1502 SN - 2352-538X UR - https://doi.org/10.2991/icmmita-15.2015.276 DO - https://doi.org/10.2991/icmmita-15.2015.276 ID - Lin2015/11 ER -