Proceedings of the 2017 5th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering (ICMMCCE 2017)

A Resistorless Voltage Reference with High-order Temperature Curvature Compensation in 55 nm CMOS Process

Authors
Kejun Wu, Yang Zhang, Qihui Zhang, Guang He, Jing Li, Ning Ning, Yang Liu, Qi Yu
Corresponding Author
Kejun Wu
Available Online September 2017.
DOI
10.2991/icmmcce-17.2017.214How to use a DOI?
Keywords
Voltage reference; resistorless; temperature curvature compensation; temperature coefficient.
Abstract

This paper presents a temperature/supply stable and resistorless voltage reference for high-precision portable electronic products. the reference obtains a good temperature coefficient over a wide temperature range through high-order curvature compensation. In order to reduce the temperature nonlinearity, the piecewise linear temperature curvature compensation circuit is used. The voltage reference is simulated with 55nm CMOS technology. It operates at the voltage of 2.5V and generates a stable voltage at 0.742V with a minimal temperature coefficient of 3.19ppm/ for temperature ranging from - 40 to 125 .

Copyright
© 2017, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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Volume Title
Proceedings of the 2017 5th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering (ICMMCCE 2017)
Series
Advances in Engineering Research
Publication Date
September 2017
ISBN
978-94-6252-381-4
ISSN
2352-5401
DOI
10.2991/icmmcce-17.2017.214How to use a DOI?
Copyright
© 2017, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Cite this article

TY  - CONF
AU  - Kejun Wu
AU  - Yang Zhang
AU  - Qihui Zhang
AU  - Guang He
AU  - Jing Li
AU  - Ning Ning
AU  - Yang Liu
AU  - Qi Yu
PY  - 2017/09
DA  - 2017/09
TI  - A Resistorless Voltage Reference with High-order Temperature Curvature Compensation in 55 nm CMOS Process
BT  - Proceedings of the 2017 5th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering (ICMMCCE 2017)
PB  - Atlantis Press
SP  - 1210
EP  - 1216
SN  - 2352-5401
UR  - https://doi.org/10.2991/icmmcce-17.2017.214
DO  - 10.2991/icmmcce-17.2017.214
ID  - Wu2017/09
ER  -