Development and Verification of A Small CMOS Digital Standard Cell Library Based on SMIC 130nm Process

DOI

10.2991/icmmcce-15.2015.62How to use a DOI?

Keywords

Standard cell library; Full adder; Optimization; Verification; P&R

Abstract

Nowadays, Semi-custom design based on the standard cells is the mainstream design method for digital IC chip. In this thesis, the standard cell library is built and verified based on the SMIC 130nm technology, especially the optimization of a 1-bit full adder cell, during which the structure and layout of the full adder in the SMIC library is analyzed. As a result, the structure and size of the adder cell are improved better, which is simulated by H-spice. The comparison shows that the optimized adder is not only smaller in area, with width decreased by 0.82 m, but also have advantages in power consumption and timing, with energy delay product reduced by 7.7% .In the end, the s298 circuit in ISCAS Benchmark89 is used as the benchmark to complete the verification method of the standard cell library.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yiwen Wang
AU  - Hang Su
AU  - Mingjiang Wang
AU  - Jipan Huang
AU  - Hao Chen
PY  - 2015/12
DA  - 2015/12
TI  - Development and Verification of A Small CMOS Digital Standard Cell Library Based on SMIC 130nm Process
BT  - Proceedings of the 4th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering 2015
PB  - Atlantis Press
SP  - 296
EP  - 302
SN  - 2352-538X
UR  - https://doi.org/10.2991/icmmcce-15.2015.62
DO  - 10.2991/icmmcce-15.2015.62
ID  - Wang2015/12
ER  -