Principle and Realization for Simulated Speed Sensor of High-speed Rail

DOI

10.2991/icecee-15.2015.169How to use a DOI?

Keywords

DDS; simulative speed sensor; FPGA; serial port communication.

Abstract

In order to test the function of the SDU module in the static environment, we design the simulative speed sensor by studying the principle of the speed sensor. We confirm the function requirements and the parameter of the simulative speed sensor by testing the speed sensor. According to the requirements, a DDS scheme based on FPGA is designed as the core of the simulative speed sensor. With the DDS scheme and the related circuit, the function of the simulative speed sensor has been approached.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Guoda Li
PY  - 2015/06
DA  - 2015/06
TI  - Principle and Realization for Simulated Speed Sensor of High-speed Rail
BT  - Proceedings of the 2015 International Conference on Electrical, Computer Engineering and Electronics
PB  - Atlantis Press
SP  - 879
EP  - 887
SN  - 2352-538X
UR  - https://doi.org/10.2991/icecee-15.2015.169
DO  - 10.2991/icecee-15.2015.169
ID  - Li2015/06
ER  -