A Hardware Design of EDT Algorithm Applied to Binary Images

DOI

10.2991/iccsee.2013.14How to use a DOI?

Keywords

distance transform, Euclidean distance, parallelization, hardware, FPGA

Abstract

In this paper, a hardware Euclidean distance transform (EDT) algorithm is proposed. The binary image data of each row are independent. For a binary image, the row distances and column distances are separately calculated. By taking the advantage of these two characteristics, a parallel EDT circuit based on the algorithm with the pipeline is designed and verified on the FPGA hardware platform. The experiment demonstrates that the time complexity of proposed EDT is N for binary image with the size of N×N .

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Hanxi Feng
AU  - Liping Tang
AU  - Peifeng Zeng
PY  - 2013/03
DA  - 2013/03
TI  - A Hardware Design of EDT Algorithm Applied to Binary Images
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 54
EP  - 59
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.14
DO  - 10.2991/iccsee.2013.14
ID  - Feng2013/03
ER  -