Research on Parallel Discrete Event Simulator based on a CPU+MIC Platform

DOI

10.2991/ameii-16.2016.172How to use a DOI?

Keywords

PDES simulator, MIC, Many Integrated Core, many-core coprocessor

Abstract

The widespread of many-core processors brings new opportunities to enhance performance of PDES applications. MIC is a relative new many-core architecture compared with the widely-used GPU. In our previous paper, experiments for evaluating performance of a PDES simulator ROSS are designed and tested on MIC and CPU respectively. However, no related works have been done on evaluation PDES simulators on CPU+MIC collaborative platform. We observe that the MPI based ROSS performs poorly, while the multi-thread ROSS is not able to work on CPU+MIC platform. We propose a PDES simulator based on a MPI+OpenMP hybrid parallel modeled ROSS which can be called as ROSS-OMPI. We use MPI to handle the interactive events between CPU and MIC, while several OpenMP threads are issued to process events in parallel inside CPU and MIC respectively. The experiment results show that the hybrid model of ROSS brings better performance.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Huilong Chen
AU  - Yiping Yao
AU  - TianLin Li
AU  - Jin Li
PY  - 2016/04
DA  - 2016/04
TI  - Research on Parallel Discrete Event Simulator based on a CPU+MIC Platform
BT  - Proceedings of the 2nd International Conference on Advances in Mechanical Engineering and Industrial Informatics (AMEII 2016)
PB  - Atlantis Press
SP  - 889
EP  - 894
SN  - 2352-5401
UR  - https://doi.org/10.2991/ameii-16.2016.172
DO  - 10.2991/ameii-16.2016.172
ID  - Chen2016/04
ER  -