Using Design Compiler Topographical Technology for Modern Process

DOI

10.2991/mecae-17.2017.48How to use a DOI?

Keywords

Interconnect Parasitics, Topographical, Physical Constraints.

Abstract

As the technology scales into deep submicron regime, accurate estimate of interconnect parasitics has become one of important factors on path delay calculation. Design Compiler Topographical technology leverages the Synopsys physical implementation solution to derive the "virtual layout" of the design, thus the tool can accurately predict and use real net capacitances instead of statistical net approximations based on wire load models (WLM). A synthesis method based on WLM mode and topographical mode for 8051 micro-controller in 90 nm technology is presented in this paper. Results show that the Design Compiler Topographical technology can accurately predict post-layout timing and ensure closed correlation to the final physical design.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Qian Liang
AU  - Ligang Hou
AU  - Jinhui Wang
PY  - 2017/03
DA  - 2017/03
TI  - Using Design Compiler Topographical Technology for Modern Process
BT  - Proceedings of the 2017 International Conference on Mechanical, Electronic, Control and Automation Engineering (MECAE 2017)
PB  - Atlantis Press
SP  - 260
EP  - 263
SN  - 2352-5401
UR  - https://doi.org/10.2991/mecae-17.2017.48
DO  - 10.2991/mecae-17.2017.48
ID  - Liang2017/03
ER  -