A 14-bit 2.5 GS/s DAC based on Multi-Clock Synchronization

DOI

10.2991/jimet-15.2015.174How to use a DOI?

Keywords

Multi-clock synchronization, quad-switch, digital-to-analog converter

Abstract

This paper presents a 14-bit 2.5GS/s current-steering segmented DAC with a new technology of synchronization, called multi-clock synchronization, which is used to optimize the timing between the internal digital and analog domains. The quad-switch architecture is also adopted to mask the code-dependent glitches. The full-scale output current can be programmed over the 10mA to 30mA range, and the typical full-scale output current is 20mA. The device is manufactured on a standard 0.18 m CMOS process and operates from 1.8V and 3.3V supplies.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Hegang Hou
AU  - Zongmin Wang
AU  - Ying Kong
AU  - Xinmang Peng
AU  - Haitao Guan
PY  - 2015/12
DA  - 2015/12
TI  - A 14-bit 2.5 GS/s DAC based on Multi-Clock Synchronization
BT  - Proceedings of the 2015 Joint International Mechanical, Electronic and Information Technology Conference
PB  - Atlantis Press
SP  - 939
EP  - 944
SN  - 2352-538X
UR  - https://doi.org/10.2991/jimet-15.2015.174
DO  - 10.2991/jimet-15.2015.174
ID  - Hou2015/12
ER  -