Power aware accuracy-guaranteed fractional bit-widths optimization
Linsheng Zhang1, Yan Zhang, Wenbiao Zhou
1Shenzhen Graduate School, Harbin Institute of Technology
Available Online December 2008.
- 10.2991/jcis.2008.24How to use a DOI?
- Fixed-point, accuracy-guaranteed, low-power, digital signal processing
A novel power aware accuracy-guaranteed fractional bit-widths optimization scheme for floating-point to fixed-point transformation of DSP algorithms is presented in this paper. Quantization-Operation-Error (QOE) model is used to construct the worst case quantization error propagation. Based on QOE, a power reduction technique is proposed to dynamically reduce switching activities in multipliers, without sacrificing required accuracy at output. The power save is nearly free.
- © 2008, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Linsheng Zhang AU - Yan Zhang AU - Wenbiao Zhou PY - 2008/12 DA - 2008/12 TI - Power aware accuracy-guaranteed fractional bit-widths optimization BT - Proceedings of the 11th Joint Conference on Information Sciences (JCIS 2008) PB - Atlantis Press SP - 138 EP - 143 SN - 1951-6851 UR - https://doi.org/10.2991/jcis.2008.24 DO - 10.2991/jcis.2008.24 ID - Zhang2008/12 ER -