Design of a SoC for Intermediate Frequency Digital Receiver

DOI

10.2991/icmit-16.2016.39How to use a DOI?

Keywords

Intermediate Frequency Digital Receiver; RF Receiver Front-end; ADC; DDC; CPU; SoC

Abstract

With the development of CMOS technology, the integration and miniaturization have become the trend of electronic devices. This paper proposes a scheme of system on chip (SoC) that realizes the monolithic integration of the intermediate frequency digital receiver based on CMOS technology, which integrates RF receiver front-end, A/D conversion, digital down conversion and baseband processing together. The chip is manufactured by 0.18um CMOS technology, and the area is 7x8mm2. The test of chip has completed within the RF reception signal range of 0.5~4GHz, The system noise of RF receiving module is below 10dB, the image rejection is greater than 40dB, the SFDR of ADC can reach to 80.22 dB, and the maximum operating frequency of DDC and CPU can arrive up to 100MHz. the test results can meet the requirements of the project evaluation index. The chip has great potential applications in the miniaturization, integration and high reliability of the electronic systems.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Lintao Liu
AU  - Jun Deng
PY  - 2016/04
DA  - 2016/04
TI  - Design of a SoC for Intermediate Frequency Digital Receiver
BT  - Proceedings of the 2016 3rd International Conference on Mechatronics and Information Technology
PB  - Atlantis Press
SP  - 217
EP  - 221
SN  - 2352-538X
UR  - https://doi.org/10.2991/icmit-16.2016.39
DO  - 10.2991/icmit-16.2016.39
ID  - Liu2016/04
ER  -