A Design of Multi-Phase Clocks Generator for CDR
Authors
Yi Shi, Yuanfu Zhao, Suge Yue, Qiang Bian, Yantu Mo
Corresponding Author
Yi Shi
Available Online April 2016.
- DOI
- 10.2991/icmemtc-16.2016.316How to use a DOI?
- Keywords
- MPCG; DLL; Gain-Boosting Chare Pump; Symmetric Load; CDR
- Abstract
As a significant component of phase interpolation based clock and data recovery circuit, the multi-phase clocks generator is used to generating multi-phase clocks for data sampling. Employing the gain-boosting charge pump and the replica bias differential voltage controlled delay line for a 1.6~2.5Gbps clock and data recovery circuit, a multi-phase clocks generator was designed and implementation in 65nm CMOS standard process with 8 output clocks. Simulation results show that: the operating frequency range of the circuit is 400~625MHz; the locking time of the circuit is 400ns@625MHz; after the phase is locked, feedback phase error < 30ps, adjacent phase error < 8ps, meeting the requirements of the clock and data recovery circuit.
- Copyright
- © 2016, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Yi Shi AU - Yuanfu Zhao AU - Suge Yue AU - Qiang Bian AU - Yantu Mo PY - 2016/04 DA - 2016/04 TI - A Design of Multi-Phase Clocks Generator for CDR BT - Proceedings of the 2016 3rd International Conference on Materials Engineering, Manufacturing Technology and Control PB - Atlantis Press SP - 1664 EP - 1669 SN - 2352-5401 UR - https://doi.org/10.2991/icmemtc-16.2016.316 DO - 10.2991/icmemtc-16.2016.316 ID - Shi2016/04 ER -