A Sample-and- Hold Circuit for a Resolution Pipelined ADC

DOI

10.2991/iceesd-18.2018.335How to use a DOI?

Keywords

sample and hold; analog-to-digital converter; olded-Cascode amplifier

Abstract

A sample-and- hold circuit for a resolution pipelined ADC is presented. The circuit uses a fully differential capacitor flip structure to reduce power consumption. Increase the gain by using an olded-cascode amplifier. Based on 0.35μm CMOS process, the Hspice simulation shows that the circuit can work correctly at 3.3v power.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yannan Zhai
AU  - Jing Li
AU  - Changhong Ding
AU  - Shuang Luan
AU  - Meishan Jin
PY  - 2018/05
DA  - 2018/05
TI  - A Sample-and- Hold Circuit for a Resolution Pipelined ADC
BT  - Proceedings of the 2018 7th International Conference on Energy, Environment and Sustainable Development (ICEESD 2018)
PB  - Atlantis Press
SP  - 1880
EP  - 1883
SN  - 2352-5401
UR  - https://doi.org/10.2991/iceesd-18.2018.335
DO  - 10.2991/iceesd-18.2018.335
ID  - Zhai2018/05
ER  -