Design of Low Power 12.5Gb/s 10:1 Multiplexer

DOI

10.2991/iccsee.2013.407How to use a DOI?

Keywords

SerDes, Multiplexer

Abstract

Design of a 10:1 multiplexer in 0.18µm CMOS technology is presented in this paper. This circuit can be used in 12.5Gb/s SerDes transmitter. The speed of traditional 10:1 is difficult to enhance due to the serial 5:1 part. In this paper, 5B/4B converter is adopted to convert the 10 channel data into 8 channel data and use tree type topology to increase the speed and save the power consumption in the data path. At the same time, phase switching divider is used to decrease the power consumption in the clock path. The core area occupies 800µm*500µm. The post simulation results show that the multiplexer can operate correctly at 12.5Gb/s, the power consumption is less than 125mW, the single-ended output peak-to-peak value is 200mV and the output jitter is less than 0.1UI.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Shenglong Zhuo
AU  - Jun Feng
PY  - 2013/03
DA  - 2013/03
TI  - Design of Low Power 12.5Gb/s 10:1 Multiplexer
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 1621
EP  - 1624
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.407
DO  - 10.2991/iccsee.2013.407
ID  - Zhuo2013/03
ER  -