Clock Network Power Saving Using Multi-Bit Flip-Flops in Multiple Voltage Island Design

DOI

10.2991/iccsee.2013.377How to use a DOI?

Keywords

Clock network, Multi-bit flip-flop, Multiple supply voltage, Level shifter, Low power

Abstract

Power consumption is an important issue in modern high-frequency and low power design. Multi-bit flip-flops are used to reduce the clock system power. The scaling with multiple supply voltage is an effective way to minimize the dynamic power consumption. In this paper, we propose an effective multi-bit flip-flops merging approach to deal with the clock network power minimization problem and an placement method to avoid placing flip-flops in the congestion bins. Moreover, the proposed approach can be applied to both single and multiple supply voltage designs. Experimental results show that our approach can reduced the clock power up to 25%. In addition, for multiple supply voltage designs, the proposed approach can reduce the number of level shifters significantly.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Jhen-Hong He
AU  - Li-Wei Huang
AU  - Jui-Hung Hung
AU  - Yu-Cheng Lin
AU  - Guo-syuan Liou
AU  - Tsai-Ming Hsieh
PY  - 2013/03
DA  - 2013/03
TI  - Clock Network Power Saving Using Multi-Bit Flip-Flops in Multiple Voltage Island Design
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 1497
EP  - 1502
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.377
DO  - 10.2991/iccsee.2013.377
ID  - He2013/03
ER  -