Run-time Leakage Reduction in Near-threshold Circuits with Gate-length Biasing Techniques

DOI

10.2991/iccsee.2013.168How to use a DOI?

Keywords

low powert, leakage reduction, gate-length biasing, near-threshold computing

Abstract

In this paper, we investigate the low leakage design method for near-threshold circuits with gate-length biasing techniques. A cost-effective gate length optimization method is presented. The basic logic gates and two full adders with gate-length biasing technique are implemented and simulated using HSPICE at 45nm CMOS process. The simulation results show that the proposed gates achieved considerable leakage reduction.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yangbo Wu
AU  - Xiaohui Fan
AU  - Haiyan Ni
PY  - 2013/03
DA  - 2013/03
TI  - Run-time Leakage Reduction in Near-threshold Circuits with Gate-length Biasing Techniques
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 662
EP  - 665
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.168
DO  - 10.2991/iccsee.2013.168
ID  - Wu2013/03
ER  -