Phase interpolation technique based on high-speed SERDES chip CDR
Authors
Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li
Corresponding Author
Meidong Lin
Available Online February 2016.
- DOI
- 10.2991/iccsae-15.2016.32How to use a DOI?
- Keywords
- phase interpolation; speed; serdes chips; the broadband rate Introduction
- Abstract
This design combines the advantages of CDR CDR circuit two structures PID and PI-based clock data is based on the structure of semi-digital dual loop recovery system. Using TSMC-0.25 m CMOS process to achieve the PLL design, the operating frequency range of 1.6-2.7GHz, and successfully applied a SERDES chip. Small footprint annular VCO wide frequency adjustment range, and can easily produce the CDR SerDes required multi-phase clock.
- Copyright
- © 2016, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Meidong Lin AU - Zhiping Wen AU - Lei Chen AU - Xuewu Li PY - 2016/02 DA - 2016/02 TI - Phase interpolation technique based on high-speed SERDES chip CDR BT - Proceedings of the 2015 5th International Conference on Computer Sciences and Automation Engineering PB - Atlantis Press SP - 160 EP - 165 SN - 2352-538X UR - https://doi.org/10.2991/iccsae-15.2016.32 DO - 10.2991/iccsae-15.2016.32 ID - Lin2016/02 ER -