Design of VLSI Digital Filters for Tolerating Transient Timing Errors

DOI

10.2991/iccnce.2013.164How to use a DOI?

Keywords

Timing errors, error-resilient design, digital filters, VLSI design.

Abstract

As the feature size of chips shrinks with semiconductor technology advancing, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and noises. With such problems, conventional worst-case designs suffer poor system performance. This paper proposes an aggressive design technique for VLSI digital filters for tolerating transient timing errors. When a timing error occurs, the system reconfigures the buffer cells of digital filters with little performance degradation. We have applied the technique to two example digital filter designs, including an FIR filter and an IIR filter. The implementation results show that our proposed designs achieve tolerance of transient timing errors with reasonable cost.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - HsinChou Chi
AU  - HsiChe Tseng
AU  - YihKai Wang
PY  - 2013/07
DA  - 2013/07
TI  - Design of VLSI Digital Filters for Tolerating Transient Timing Errors
BT  - Proceedings of the International Conference on Computer, Networks and Communication Engineering (ICCNCE 2013)
PB  - Atlantis Press
SP  - 662
EP  - 665
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccnce.2013.164
DO  - 10.2991/iccnce.2013.164
ID  - Chi2013/07
ER  -