Proceedings of the 2016 International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2016)

High-speed and Huge-capacity Data Cache System Based on FPGA

Authors
Fei Gao, Wenge Chang, Xiangyang Li
Corresponding Author
Fei Gao
Available Online September 2016.
DOI
https://doi.org/10.2991/iccia-16.2016.83How to use a DOI?
Keywords
Cache; High-speed; Huge-capacity; DDR3; RapidIO.
Abstract
Aiming at the high-speed and huge-capacity data cache and transmission caused by real-time signal processor for high-resolution SAR, this paper presents a design for the high-speed and huge-capacity data acquisition system based on DDR3 SDRAM and RapidIO. Data cache is realized by MIG3.92 IP core in Xilinx Virtex_6 series FPGA. Data Transmission is realized by RapidIO IP core and GTX. The testing results show that the maximum write rate of DDR3 memory is 3120MB/s and the transmission rate of RapidIO interface is 1800MB/s.
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Proceedings
2016 International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2016)
Part of series
Advances in Computer Science Research
Publication Date
September 2016
ISBN
978-94-6252-240-4
ISSN
2352-538X
DOI
https://doi.org/10.2991/iccia-16.2016.83How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Fei Gao
AU  - Wenge Chang
AU  - Xiangyang Li
PY  - 2016/09
DA  - 2016/09
TI  - High-speed and Huge-capacity Data Cache System Based on FPGA
BT  - 2016 International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2016)
PB  - Atlantis Press
SP  - 449
EP  - 453
SN  - 2352-538X
UR  - https://doi.org/10.2991/iccia-16.2016.83
DO  - https://doi.org/10.2991/iccia-16.2016.83
ID  - Gao2016/09
ER  -