Design of IRIG-B Code Encoder Based on SOPC

DOI

10.2991/iccasm.2012.26How to use a DOI?

Keywords

IRIG-B code, SOPC, NIOSII, Time coding

Abstract

Aiming at the complexity of time unified hardware architecture, this paper presents the design scheme of IRIG-B encoder and system control based on SOPC. The NIOSII processor is configured with NIOSII IDE. Firstly, the design of IRIG-B(DC) coding module is accomplished to realize with Verilog HDL, and then IRIG-B(AC) coding module is completed successfully through the D\A conversion on the basis of IRIG-B(DC) code. The experiment result shows that the encoder can stably and reliably produce a standard IRIG-B code, and satisfy the application requirements.

Copyright

© 2012, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Qiaoyu Xu
AU  - Xing Wang
PY  - 2012/08
DA  - 2012/08
TI  - Design of IRIG-B Code Encoder Based on SOPC
BT  - Proceedings of the 2012 International Conference on Computer Application and System Modeling (ICCASM 2012)
PB  - Atlantis Press
SP  - 103
EP  - 106
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccasm.2012.26
DO  - 10.2991/iccasm.2012.26
ID  - Xu2012/08
ER  -