TMR-Based Soft Error Tolerance Techniques in ASIC Design

DOI

10.2991/icadme-16.2016.76How to use a DOI?

Keywords

TMR; Soft Error; SEU; ASIC.

Abstract

With the evolution of process and innovation of design technology, it makes soft errors on the reliability of the integrated circuit to bring more and more serious threat. Space radiation environment caused by high-energy particles Single Event Upset (SEU) event seriously affected the reliability of the integrated circuit. On the basis of the process level and layout-level and other complex soft error tolerance techniques, a redundant structure can achieve shielding effect of Single Event Upset. Triple modular redundant structure is easy to implement, also makes the anti-radiation performance of the entire circuit has been greatly improved.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xin He
AU  - Xu Huang
AU  - Yujing Li
PY  - 2017/07
DA  - 2017/07
TI  - TMR-Based Soft Error Tolerance Techniques in ASIC Design
BT  - Proceedings of the 2016 6th International Conference on Advanced Design and Manufacturing Engineering (ICADME 2017)
PB  - Atlantis Press
SP  - 455
EP  - 458
SN  - 2352-5401
UR  - https://doi.org/10.2991/icadme-16.2016.76
DO  - 10.2991/icadme-16.2016.76
ID  - He2017/07
ER  -