A Novel Clock circuit used in Time-Interleaved ADC
- 10.2991/ic3me-15.2015.178How to use a DOI?
- A/D converter, T-I ADC, Clock, Timing mismatch.
This paper presents a new type of clock system based on standard CMOS 0.18 m, 1.8V process. It can be used for 14bit, 500 MHz sampling frequency, time interleaving (TI) ADC. The clock edge reassignment technique has been introduced in this paper. Simulation has been run in Spectre under Cadence platform. The result shows that this clock circuit is especially useful in a 14bit, 500MHz sampling frequency high speed TI ADC and the timing mismatch is less than roughly 2ps , which meets the design requirement.
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Xiaofeng Shen AU - Liang Li AU - Mingyuan Xu AU - Xi Chen PY - 2015/08 DA - 2015/08 TI - A Novel Clock circuit used in Time-Interleaved ADC BT - Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering PB - Atlantis Press SP - 930 EP - 933 SN - 2352-5401 UR - https://doi.org/10.2991/ic3me-15.2015.178 DO - 10.2991/ic3me-15.2015.178 ID - Shen2015/08 ER -