Clock Tree Synthesis in ASIC Back-end Design

DOI

10.2991/eia-17.2017.35How to use a DOI?

Keywords

clock tree synthesis (CTS); clock skew; clock closure; clock cell area

Abstract

Based on the Synopsys physical design tool IC Compiler, taking the design of BES6799 chip under SMIC 0.18 m Logic 1P5M process as an example, this paper analyzed and compared the clock skew and clock cell area of clock trees which are built by three methods, such as inserting inverter, buffer, combination of both. It was found that the clock tree completed with buffers has a better clock skew and the clock cell areas are almost the same. So buffer is selected as the clock delay cell to build clock tree. In order to further reduce the clock skew and then make timing closure, the clock tree synthesis method which the important clocks are synthesized first is proposed. It was shown that the method can effectively reduce the clock skew and clock cell area. Based on the above methods, the chip was finally taped out in SMIC.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Hongyan CHAI
AU  - Peiyuan WAN
AU  - Yue MA
PY  - 2017/07
DA  - 2017/07
TI  - Clock Tree Synthesis in ASIC Back-end Design
BT  - Proceedings of the 2017 International Conference on Electronic Industry and Automation (EIA 2017)
PB  - Atlantis Press
SP  - 164
EP  - 167
SN  - 1951-6851
UR  - https://doi.org/10.2991/eia-17.2017.35
DO  - 10.2991/eia-17.2017.35
ID  - CHAI2017/07
ER  -