Study STATCOM with Small Time-Step Simulation on FPGAs

DOI

10.2991/cisia-15.2015.62How to use a DOI?

Keywords

FPGA; small time-step; STATCOM; simulation; modelling

Abstract

STATCOMs are installed in Power grids all over the world with its powerful reactive power support and other various functions. The STATCOM simulation technology is also promoting greatly. FPGAs, as a newly processor, are considered in STATCOM simulation to realize the small time-step, which could increase precision greatly. This paper deeply studies FPGA implementation in STATCOM simulation. Firstly, the modelling of STATCOM on FPGA is briefly studied. The modelling includes electric topology and control schemes. Then, the realization of FPGA simulation demonstrates the structure of this FPGAs simulator. Finally, the paper will carry on multiple tests and comparison to show the validation and advantage of STATCOM simulation with small time-step on FPGAs.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - M.M Xu
AU  - W. Gu
AU  - Q. Fan
AU  - J. Qin
AU  - Q. Mu
AU  - X. Zhang
AU  - X.X. Wang
PY  - 2015/06
DA  - 2015/06
TI  - Study STATCOM with Small Time-Step Simulation on FPGAs
BT  - Proceedings of the International Conference on Computer Information Systems and Industrial Applications
PB  - Atlantis Press
SP  - 233
EP  - 236
SN  - 2352-538X
UR  - https://doi.org/10.2991/cisia-15.2015.62
DO  - 10.2991/cisia-15.2015.62
ID  - Xu2015/06
ER  -