Proceedings of the 2018 International Symposium on Communication Engineering & Computer Science (CECS 2018)

The Storage Structure of Convolutional Neural Network Reconfigurable Accelerator Based on ASIC

Authors
Jingqun Li, Mingjiang Wang, Hongli Pan
Corresponding Author
Jingqun Li
Available Online July 2018.
DOI
10.2991/cecs-18.2018.56How to use a DOI?
Keywords
Convolutional Neural Network, CNNs, accelerator, CMOS, AlexNet.
Abstract

With the development of deep convolutional neural networks (CNNs), it can be achieved higher accuracy in many aspects, including computer vision, speech and natural language processing. Performance efficiency of CNN at the hardware level requires overcoming the large calculation-related problems, so memory bandwidth and power budgets, should be in economical limits. CNNs models also adopts different kernel sizes, depends on the application nature, therefore it is important for designed architecture to be reconfigurable. In this work, we propose a new high-performance multi-precision reconfigurable architecture (MPRA) and optimize it for recent CNNs using 3×3/5×5/7×7 convolution such as AlexNet, GoogLeNet and ResNet with 16-bit fixed and 8-bit fixed precision. The architecture synthesized on 65 nm CMOS technologies achieves average performance (GOPS) of 276.5 in 16bit×16bit and 1105.9 in 8bit×8bit mode, running at 640 MHz and 1 V with a power dissipation of 599 mW respectively. Compared to state-of-the-art designs, the proposed architecture achieves 2.36× energy efficiency, 2.4× to 6.8× area efficiency, and 16.3% to 27.4% higher computational efficiency for AlexNet benchmarked reference.

Copyright
© 2018, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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Volume Title
Proceedings of the 2018 International Symposium on Communication Engineering & Computer Science (CECS 2018)
Series
Advances in Computer Science Research
Publication Date
July 2018
ISBN
10.2991/cecs-18.2018.56
ISSN
2352-538X
DOI
10.2991/cecs-18.2018.56How to use a DOI?
Copyright
© 2018, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Cite this article

TY  - CONF
AU  - Jingqun Li
AU  - Mingjiang Wang
AU  - Hongli Pan
PY  - 2018/07
DA  - 2018/07
TI  - The Storage Structure of Convolutional Neural Network Reconfigurable Accelerator Based on ASIC
BT  - Proceedings of the 2018 International Symposium on Communication Engineering & Computer Science (CECS 2018)
PB  - Atlantis Press
SP  - 323
EP  - 327
SN  - 2352-538X
UR  - https://doi.org/10.2991/cecs-18.2018.56
DO  - 10.2991/cecs-18.2018.56
ID  - Li2018/07
ER  -