Design and Implementation of SPARC V8 CPU Simulator in Virtualized Verification System
Yongchao Tao, Wencheng Xiang, Xianghu Wu
Available Online December 2017.
- https://doi.org/10.2991/anit-17.2018.31How to use a DOI?
- SPARC, all-digital simulation, instruction set simulation, interpretive execution.
- The aim of this paper is to design and develop a simulator with high efficiency and flexibility for the SPARC processor which is widely used in present domestic aerospace industry based on the virtualized verification system. Firstly, the feature of SPARC instruction set architecture is studied and the simulation of its register file, execution of instruction and handling of trap is implemented wtih C programing languge respectively. Further, the high performance general graphics processor is explored to gain more performance improvement and the pre-decoding functions are eventually realized with CUDA and obtain considerable seed up.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Yongchao Tao AU - Wencheng Xiang AU - Xianghu Wu PY - 2017/12 DA - 2017/12 TI - Design and Implementation of SPARC V8 CPU Simulator in Virtualized Verification System BT - 2017 International Seminar on Artificial Intelligence, Networking and Information Technology (ANIT 2017) PB - Atlantis Press SP - 179 EP - 183 SN - 1951-6851 UR - https://doi.org/10.2991/anit-17.2018.31 DO - https://doi.org/10.2991/anit-17.2018.31 ID - Tao2017/12 ER -