FPGA Realization of Duffing Chaotic Oscillator Based on Runge-Kutta Algorithm

DOI

10.2991/amcce-17.2017.51How to use a DOI?

Keywords

Runge-Kutta algorithm, Duffing chaotic oscillator, FPGA.

Abstract

Duffing chaotic oscillator shows good detection and communication effect since it is sensitive to initial condition and has good resistance to noise. This paper presents an effective method for the digital hardware realization of Duffing chaotic oscillator on FPGA by using the Verilog HDL hardware description language directly and the fourth-order Runge-Kutta algorithm. Firstly, deduces the iterative process of Duffing chaotic oscillator according to the fourth-order Runge-Kutta algorithm. Secondly, uses the Verilog HDL language directly to the hardware realization of chaotic oscillator. Finally, outputs the generated signal on FPGA by the designed high-speed DAC. This method solves the problem that Duffing chaotic oscillator cannot realize the strict matching in the analog circuit because of the parameter errors due to component manufacturing and aging. This method also consumes fewer FPGA resources and the generated Duffing chaotic oscillator can be invoked easily by other modules for signal detection or communication. As a result it is practicable for use.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Beiming Li
AU  - Yixin Xu
AU  - HongYang Shi
AU  - Wei Xue
PY  - 2017/03
DA  - 2017/03
TI  - FPGA Realization of Duffing Chaotic Oscillator Based on Runge-Kutta Algorithm
BT  - Proceedings of the 2017 2nd International Conference on Automation, Mechanical Control and Computational Engineering (AMCCE 2017)
PB  - Atlantis Press
SP  - 293
EP  - 296
SN  - 2352-5401
UR  - https://doi.org/10.2991/amcce-17.2017.51
DO  - 10.2991/amcce-17.2017.51
ID  - Li2017/03
ER  -