An Optimized Sample Rate Converter for a software radio receiver on FPGA
- Abstract
Abstract-Sample Rate Conversion(SRC) and channelization are the two necessary tasks to be implemented for the design of a radio receiver. For a multi-standard software radio with a very high intermediate frequency(IF), which is of the order of 80MHz and above, the implementation of a sample rate converter is highly computationally intensive. In a multi-standard radio receiver the phenomenon of bandpass sampling over samples the required channel with high over sampling ratios(OSR). In this paper we present an optimized implementation of SRC suitable for down conversion of various wireless standards ranging from wireless LAN WiMAX 802.16 to GSM900 system by the method of factorization. A mixer is designed using CORDIC algorithm in the IF stage and a decimator incorporates Cascaded Integrated Comb(CIC) lter as a component for sample rate conversion. We have optimized the CIC lter by reducing the number of bits in CIC lters from one stage to another. Comparison of the hardware resource utilization of this architecture with non-optimized CIC lter reported more than twenty percent reduction in hardware.
- Copyright
- © 2013, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Ashok Agarwal AU - B. Lakshmi PY - 2013/04 DA - 2013/04 TI - An Optimized Sample Rate Converter for a software radio receiver on FPGA BT - Proceedings of the Conference on Advances in Communication and Control Systems (CAC2S 2013) PB - Atlantis Press SP - 115 EP - 119 SN - 1951-6851 UR - https://www.atlantis-press.com/article/6288 ID - Agarwal2013/04 ER -