9th Joint International Conference on Information Sciences (JCIS-06)

A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes

Authors
Chin-Fa Hsieh 0, Tsung-Han Tsai, Neng-Jye Hsu, Chih-Hung Lai
Corresponding author
Chin-Fa Hsieh
0China Institute of Technology, Taipei, Taiwan
DOI
https://doi.org/10.2991/jcis.2006.20How to use a DOI?
Keywords
lifting, discrete wavelet transform
Abstract
In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.
Copyright
© The authors. This article is distributed under the terms of the Creative Commons Attribution License 4.0, which permits non-commercial use, distribution and reproduction in any medium, provided the original work is properly cited. See for details: https://creativecommons.org/licenses/by-nc/4.0/
Open Access | Under Creative Commons license CC BY-NC 4.0

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@inproceedings{Hsieh2006,
  title={A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes},
  author={Hsieh, Chin-Fa and Tsai, Tsung-Han and Hsu, Neng-Jye and Lai, Chih-Hung},
  year={2006},
  booktitle={9th Joint International Conference on Information Sciences (JCIS-06)},
  issn={1951-6851},
  isbn={978-90-78677-01-7},
  url={http://dx.doi.org/10.2991/jcis.2006.20},
  doi={10.2991/jcis.2006.20},
  publisher={Atlantis Press}
}
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