An Optimized Scheme for High-speed Data Interaction Based on TI-C6678 Multi-core DSP

DOI

10.2991/iccnce.2013.165How to use a DOI?

Keywords

Data interaction, GDMA, High-speed, Multi-core DSP, Bridge memory.

Abstract

The performance of data interaction between different memories has become a significant factor in the complex embedded systems with the huge increase of processing needs, especially between internal chip-on memory and external memory. This paper advances a constructive optimized scheme named global direct memory access (GDMA) for high-speed data interaction in the multi-core digital signal processor (DSP) systems. Furmore, we give important recommendations to actualize software programming optimization of GDMA from three aspects.This scheme is based on the key technique of enhanced direct memory access versions3 (EDMA3), quick direct memory access (QDMA) and internal direct memory access (IDMA). This scheme can enhance the peak speed of data interaction between local memories by 53.8% and 2.5% averagely for some situations using QDMA compared EDMA3. By establishing the bridge memory area, the speed from level-1 data memory to external memory is optimized by 15.3% maximumly. The multi-core DSP system can achieve the performance of high-speed data interaction at around 5GBps to meet user expectations.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Baoyu Su
AU  - Zhiyong Xu
AU  - Renjie Niu
PY  - 2013/07
DA  - 2013/07
TI  - An Optimized Scheme for High-speed Data Interaction Based on TI-C6678 Multi-core DSP
BT  - Proceedings of the International Conference on Computer, Networks and Communication Engineering (ICCNCE 2013)
PB  - Atlantis Press
SP  - 666
EP  - 669
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccnce.2013.165
DO  - 10.2991/iccnce.2013.165
ID  - Su2013/07
ER  -